September 24, 2026 / SemiMedia / — Lattice Semiconductor has introduced the Mach-N2 FPGA family, expanding its system control and security portfolio with devices built on the Lattice Nexus 2 small FPGA platform and integrating non-volatile flash, a hardware Root of Trust and post-quantum cryptography.

Mach-N2 is designed for system control, security monitoring, power sequencing and platform management across compute, communications and industrial infrastructure. The family offers up to twice the logic density of previous devices and higher SERDES bandwidth for direct connectivity to modern SoCs and processors.

For security, Mach-N2 supports CNSA 2.0-compliant post-quantum algorithms including ML-DSA, LMS and XMSS for authentication, as well as ML-KEM for key exchange. The devices also support crypto agility with field-updatable algorithms and anti-rollback protection, allowing security functions to be updated over long system lifecycles.

The family includes PUF-derived device identity with DICE and SPDM attestation for platform and supply-chain integrity. Classical cryptography support includes AES-256-GCM, 521-bit ECC and 4096-bit RSA, with APIs accessible during runtime.

On-chip non-volatile flash stores configuration data internally, helping prevent external access to the configuration bitstream and User Flash Memory. Lattice said a 220K-system-logic-cell Mach-N2 device can fully configure in under 30 milliseconds and can store up to three configuration images, including primary, secondary and golden images for recovery.

For high-speed connectivity, Mach-N2 supports PCIe 4.0, 10G Ethernet and SERDES speeds of up to 16Gbps, targeting control and management functions in servers, networking equipment and industrial systems.

The Mach-N2 family is available for order now, and Lattice said samples have already shipped to selected compute and communications customers.