Semiconductor packaging constraints are spreading beyond advanced technologies such as CoWoS as rising AI server demand puts increasing pressure on traditional packaging capacity. Industry sources said several outsourced semiconductor assembly and test providers have warned customers that the traditional packaging capacity gap could exceed 20% in 2027, with limited wire bonder supply emerging as a key expansion bottleneck.

AI servers require more than GPUs and HBM. They also contain large numbers of CPUs, networking chips, power management ICs, controllers and other peripheral devices, many of which continue to use mature packaging technologies including wire bonding, QFN and BGA.

As AI server shipments increase, recovering demand from memory, communications and industrial markets is adding further pressure on traditional packaging lines. ASMPT has also reported stronger demand for wire and die bonding applications as AI infrastructure investment expands and OSAT utilization rises.

At the same time, major OSAT providers have been directing more capital and equipment toward advanced packaging for AI and high-performance computing applications. Investment in traditional packaging had remained relatively cautious when demand was more stable, leaving suppliers with limited flexibility as utilization increases.

K&S and ASMPT are among the major suppliers of wire bonding equipment. Although wire bonding is a mature technology, production lines depend on established process parameters, automation configurations, maintenance systems and customer qualifications. Switching equipment platforms can therefore require additional process validation and customer approval, limiting the ability of OSATs to add capacity quickly.

Tighter capacity is also beginning to affect pricing. Some smaller IC design companies have reportedly turned to packaging providers in mainland China for additional capacity, but they are also encountering higher quotations and new production requirements.

After wafer capacity and advanced packaging, traditional packaging is emerging as another resource that chip designers may need to secure earlier. If wire bonder deliveries and equipment installation cannot keep pace with demand, mature packaging capacity could tighten further into 2027.