May 29, 2026 /SemiMedia/ — ASE Technology Holding’s semiconductor packaging subsidiary ASE announced it has developed what it describes as the industry’s first automated 310 mm × 310 mm panel-level packaging (PLP) production line, with mass production scheduled to begin in the first half of 2027.

The new platform represents a major step in the transition from conventional wafer-level packaging to panel-level manufacturing and is designed to support ASE’s FOCoS and FOCoS-Bridge advanced packaging technologies.

As AI accelerators, chiplet architectures, ASICs and high-bandwidth memory (HBM) continue to drive demand for more advanced semiconductor integration, packaging technologies have become increasingly critical to overall system performance. ASE said its panel-level platform is designed to enable higher bandwidth, lower latency interconnects while supporting future trillion-transistor system-in-package (SiP) architectures.

The production line supports 310 mm × 310 mm panels and delivers line/space capabilities of 2/2 µm and 8/8 µm for FOCoS and FOCoS-Bridge applications respectively. Compared with traditional circular wafers, the rectangular panel format provides up to 96,100 mm² of usable area, improving die utilization and material efficiency.

ASE said panel-level packaging addresses several longstanding challenges facing advanced packaging technologies, including increasing interposer sizes and declining efficiency in wafer-based manufacturing approaches. Larger panel formats can improve throughput, shorten production cycles and support more complex multi-die integration.

The company expects the platform to serve applications across AI data centers, high-performance computing, networking equipment, premium gaming systems and edge AI devices, where demand for larger package sizes and higher I/O density continues to rise.

ASE Vice President of R&D Dr. Hung Chih-Pin said the automated panel-level manufacturing platform significantly improves scalability and production efficiency while supporting future AI and HPC performance requirements.

Executive Vice President Yin Chang added that panel-level packaging will play a key role in enabling the next wave of AI innovation, as future computing performance increasingly depends on both advanced silicon technologies and advanced packaging solutions.