February 27, 2026 /SemiMedia/ — Broadcom said it expects shipments of chips based on its stacking technology to reach at least 1 million units by 2027, setting a new product and revenue milestone as demand for AI computing rises.

Harish Bharadwaj, vice president of product marketing at Broadcom, said the company’s approach stacks two dies together to create a tightly connected structure that improves data transfer speed between chips while lowering power use.

Fujitsu is expected to be the first customer to adopt the design and is currently preparing engineering samples for testing. The Japanese company plans to begin production of the stacked, or 3D, data center chip later this year. Broadcom noted the 1-million-unit forecast also includes several additional designs now under development.

Bharadwaj said the technology allows customers to build more powerful and energy-efficient processors to handle fast-growing AI workloads. He added that most of Broadcom’s key customers are already evaluating or adopting the stacked architecture.

Broadcom typically works with partners rather than designing full AI processors on its own. The company collaborates with Google on tensor processing units and is also working with OpenAI on custom internal processors. Its engineers focus on turning early chip concepts into physical layouts ready for foundry manufacturing.

Driven by these custom programs, Broadcom’s AI chip business has expanded quickly. The company expects AI semiconductor revenue to double year over year to about $8.2 billion in the first fiscal quarter, strengthening its position against Nvidia and AMD.

Fujitsu’s new data center chip will be manufactured using TSMC’s 2nm process and combined with a 5nm die through advanced packaging. The foundry will bond the upper and lower chips during production.

Broadcom said two new stacked-chip products are planned for the second half of 2026, followed by three additional samples in 2027. The company has spent roughly five years building the technology platform and is working toward designs that could support up to eight stacked layers, with two chips in each layer.