Microchip Technology Inc. recently announced the new META-DX2+ PHY family, the industry's first solution to integrate 1.6T (terabits per second) wire-speed end-to-end encryption and port aggregation for use in enterprise Ethernet switches, security appliances, security appliances, cloud interconnect routers and optical transport systems .
“The introduction of four new META-DX2+ Ethernet PHYs demonstrates our commitment to supporting the industry transition to 112G PAM4 connectivity powered by our META-DX retimer and PHY portfolio. In conjunction with our META-DX2L retimer, we now offer a complete chipset for all connectivity needs from retiming, gearboxing, to advanced PHY functionality,” said Babak Samimi, corporate vice president of Microchip’s communications business unit. “By offering both hardware and software footprint compatibility, our customers can leverage architectural designs across their enterprise, data center, and service provider switching and routing systems that can offer pay-as-you-need enablement of advanced features including end-to-end security, multi-rate port aggregation, and precision timestamping via a software subscription model.”
The META-DX2+’s configurable 1.6T datapath architecture outperforms the next near competitors by 2x in total gearbox capacity and hitless 2:1 protection switch mux modes enabled by its unique ShiftIO capability. The flexible XpandIO port aggregation capabilities optimize router/switch port utilization when supporting low-rate traffic. Also, the devices include IEEE® 1588 Class C/D Precision Time Protocol (PTP) support for accurate nanosecond timestamping required for 5G and enterprise business critical services. By offering a portfolio of footprint-compatible retimer and advanced PHYs with encryption options, Microchip enables developers to expand their designs to add MACsec and IPsec based on a common board design and Software Development Kit (SDK).
“As the industry transitions to a 112G PAM4 serial ecosystem for high-density routers and switches, line-rate encryption and efficient use of port capacity becomes increasingly important,” said Alan Weckel, founder and technology analyst at 650 Group, LLC. “Microchip’s META-DX2+ family will play an important role in enabling MACsec and IPsec encryption, optimizing port capacity with port aggregation, and flexibly connecting routing/switching silicon to multi-rate 400G and 800G optics.”
The META-DX2+ family is expected to sample during the fourth calendar quarter of 2022. For additional information visit the META-DX2+ webpage.
