According to reports, TSMC is planning to set up a new R&D center in Taiwan to focus on 2nm chip research.
The report pointed out that the new R&D center will operate an advanced production line and have 8,000 engineers.
On August 25th, TSMC President Dr. C.C. Wei talked about TSMC’s future 4nm process, 3nm process and the new N12e special process at the TSMC technology seminar.
TSMC’s industry-leading 5 nanometer (nm) N5 technology entered volume production this year and defect density reduction is proceeding faster than the previous generation as capacity continues to ramp. N5 provides a 15% performance gain or a 30% power reduction, and up to 80% logic density gain over the preceding N7 technology. Building on the original N5, TSMC plans to ramp an enhanced N5P version in 2021, offering an additional 5% speed gain and 10% power improvement.
TSMC also offered a preview of the latest member of the 5nm family – the N4 process. N4 will provide further improvements in performance, power and density to cover a wide range of product needs. In addition to process simplification with reduced mask layers, N4 also offers a straightforward migration path with the ability to leverage the comprehensive 5nm design ecosystem. The N4 process is scheduled to start risk production in fourth quarter of 2021, with volume production in 2022.
Looking ahead to the next generation, TSMC’s N3 process is on track to become the most advanced logic technology in the world featuring up to 15% performance gain, up to 30% power reduction, and a logic density gain up to 70% over N5.
